spinn_extra.h

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/*
 * Copyright (c) 2019 The University of Manchester
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
// ------------------------------------------------------------------------
// ------------------------------------------------------------------------
 
#ifndef __SPINN_EXTRA_H__
#define __SPINN_EXTRA_H__
 
#include <spinnaker.h>
#include <stdbool.h>
 
#ifndef DOXYGEN
// Hack for better naming in doxygen while avoiding warnings when building
#define DOXYNAME(x)     /* nothing */
#endif
 
#if defined(__GNUC__) && __GNUC__ < 6
// This particular warning (included in -Wextra) is retarded wrong for client
// code of this file. Only really a problem on Travis.
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
#endif // __GNUC__
 
#define ASSERT_WORD_SIZED(type_ident) \
    static inline void __static_word_sized_assert_ ## type_ident (void) { \
        _Static_assert(sizeof(type_ident) == sizeof(uint),              \
                #type_ident " must be the same size as a word");        \
    }
 
// ---------------------------------------------------------------------
// 1. Chip Organization
 
// No registers
 
// ---------------------------------------------------------------------
// 2. System Architecture
 
// No registers
 
// ---------------------------------------------------------------------
// 3. ARM968 Processing Subsystem
 
// No registers
 
// ---------------------------------------------------------------------
// 4. ARM 968
 
// No special registers here
 
// ---------------------------------------------------------------------
 
typedef void (*vic_interrupt_handler_t) (void);
 
typedef union {
    struct DOXYNAME(interrupt_bits) {
        uint watchdog : 1;
        uint software : 1;
        uint comm_rx : 1;
        uint comm_tx : 1;
        uint timer1 : 1;
        uint timer2 : 1;
        uint cc_rx_ready : 1;
        uint cc_rx_parity_error : 1;
        uint cc_rx_framing_error : 1;
        uint cc_tx_full : 1;
        uint cc_tx_overflow : 1;
        uint cc_tx_empty : 1;
        uint dma_done : 1;
        uint dma_error : 1;
        uint dma_timeout : 1;
        uint router_diagnostic : 1;
        uint router_dump : 1;
        uint router_error : 1;
        uint cpu : 1;
        uint ethernet_tx : 1;
        uint ethernet_rx : 1;
        uint ethernet_phy : 1;
        uint slow_clock : 1;
        uint cc_tx_not_full : 1;
        uint cc_rx_mc : 1;
        uint cc_rx_p2p : 1;
        uint cc_rx_nn : 1;
        uint cc_rx_fr : 1;
        uint int0 : 1;
        uint int1 : 1;
        uint gpio8 : 1;
        uint gpio9 : 1;
    };
    uint value;
} vic_mask_t;
 
typedef struct {
    const vic_mask_t irq_status;
    const vic_mask_t fiq_status;
    const vic_mask_t raw_status;
    vic_mask_t int_select;
    vic_mask_t int_enable;
    vic_mask_t int_disable;
    vic_mask_t soft_int_enable;
    vic_mask_t soft_int_disable;
    bool protection;
    // padding
    const uint _padding[3];
    vic_interrupt_handler_t vector_address;
    vic_interrupt_handler_t default_vector_address;
} vic_control_t;
 
typedef struct {
    uint source : 5;
    uint enable : 1;
    // padding
    uint : 26;
} vic_vector_control_t;
 
ASSERT_WORD_SIZED(vic_mask_t);
ASSERT_WORD_SIZED(vic_interrupt_handler_t);
ASSERT_WORD_SIZED(vic_vector_control_t);
 
static volatile vic_control_t *const vic_control =
        // NB unbuffered!
        (vic_control_t *) VIC_BASE_UNBUF;
static volatile vic_interrupt_handler_t *const vic_interrupt_vector =
        (vic_interrupt_handler_t *) (VIC_BASE + 0x100);
static volatile vic_vector_control_t *const vic_interrupt_control =
        (vic_vector_control_t *) (VIC_BASE + 0x200);
 
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint one_shot : 1;
    uint size : 1;
    uint pre_divide : 2;
    // padding
    uint : 1;
    uint interrupt_enable : 1;
    uint periodic_mode : 1;
    uint enable : 1;
    // padding
    uint : 24;
} timer_control_t;
 
enum timer_pre_divide {
    TIMER_PRE_DIVIDE_1 = 0,
    TIMER_PRE_DIVIDE_16 = 1,
    TIMER_PRE_DIVIDE_256 = 2
};
 
typedef struct {
    uint status : 1;
    // padding
    uint : 31;
} timer_interrupt_status_t;
 
typedef struct {
    uint load_value;
    const uint current_value;
    timer_control_t control;
    uint interrupt_clear;
    const timer_interrupt_status_t raw_interrupt_status;
    const timer_interrupt_status_t masked_interrupt_status;
    uint background_load_value;
    // padding
    uint _dummy;
} timer_controller_t;
 
ASSERT_WORD_SIZED(timer_control_t);
ASSERT_WORD_SIZED(timer_interrupt_status_t);
 
static volatile timer_controller_t *const timer1_control =
        (timer_controller_t *) TIMER1_BASE;
static volatile timer_controller_t *const timer2_control =
        (timer_controller_t *) TIMER2_BASE;
 
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint _zeroes : 2;
    uint length_words : 15;
    // padding
    uint : 2;
    uint direction : 1;
    uint crc : 1;
    uint burst : 3;
    uint width : 1;
    uint privilege : 1;
    uint transfer_id : 6;
} dma_description_t;
 
enum dma_direction_t {
    DMA_DIRECTION_READ,
    DMA_DIRECTION_WRITE
};
 
enum dma_transfer_unit_t {
    DMA_TRANSFER_WORD,
    DMA_TRANSFER_DOUBLE_WORD
};
 
typedef struct {
    uint uncommit : 1;
    uint abort : 1;
    uint restart : 1;
    uint clear_done_int : 1;
    uint clear_timeout_int : 1;
    uint clear_write_buffer_int : 1;
    // padding
    uint : 26;
} dma_control_t;
 
typedef struct {
    uint transferring : 1;
    uint paused : 1;
    uint queued : 1;
    uint write_buffer_full : 1;
    uint write_buffer_active : 1;
    // padding
    uint : 5;
    uint transfer_done : 1;
    uint transfer2_done : 1;
    uint timeout : 1;
    uint crc_error : 1;
    uint tcm_error : 1;
    uint axi_error : 1;
    uint user_abort : 1;
    uint soft_reset : 1;
    // not allocated
    uint : 2;
    uint write_buffer_error : 1;
    // padding
    uint : 3;
    uint processor_id : 8;
} dma_status_t;
 
typedef struct {
    uint bridge_buffer_enable : 1;
    // padding
    uint : 9;
    uint transfer_done_interrupt : 1;
    uint transfer2_done_interrupt : 1;
    uint timeout_interrupt : 1;
    uint crc_error_interrupt : 1;
    uint tcm_error_interrupt : 1;
    uint axi_error_interrupt : 1;
    uint user_abort_interrupt : 1;
    uint soft_reset_interrupt : 1;
    // not allocated
    uint : 2;
    uint write_buffer_error_interrupt : 1;
    // padding
    uint : 10;
    uint timer : 1;
} dma_global_control_t;
 
typedef struct {
    uint _zeroes : 5;
    uint value : 5;
    // padding
    uint : 22;
} dma_timeout_t;
 
typedef struct {
    uint enable : 1;
    uint clear : 1;
    // padding
    uint : 30;
} dma_stats_control_t;
 
typedef struct {
    // padding
    const uint _unused1[1];
    void *sdram_address;
    void *tcm_address;
    dma_description_t description;
    dma_control_t control;
    const dma_status_t status;
    dma_global_control_t global_control;
    const uint crcc;
    const uint crcr;
    dma_timeout_t timeout;
    dma_stats_control_t statistics_control;
    // padding
    const uint _unused2[5];
    const uint statistics[8];
    // padding
    const uint _unused3[41];
    const void *current_sdram_address;
    const void *current_tcm_address;
    const dma_description_t current_description;
    // padding
    const uint _unused4[29];
    uint crc_polynomial[32];
} dma_t;
 
ASSERT_WORD_SIZED(dma_description_t);
ASSERT_WORD_SIZED(dma_control_t);
ASSERT_WORD_SIZED(dma_status_t);
ASSERT_WORD_SIZED(dma_global_control_t);
ASSERT_WORD_SIZED(dma_timeout_t);
ASSERT_WORD_SIZED(dma_stats_control_t);
 
static volatile dma_t *const dma_control = (dma_t *) DMA_BASE;
 
 
// ---------------------------------------------------------------------
 
typedef union {
    struct DOXYNAME(common) {
        uchar parity : 1;
        uchar payload : 1;
        uchar timestamp : 2;
        // padding
        uchar : 2;
        uchar type : 2;
    };
    struct DOXYNAME(mc) {
        // padding
        uchar : 4;
        uchar emergency_routing : 2;
        // padding
        uchar : 2;
    } mc;
    struct DOXYNAME(p2p) {
        // padding
        uchar : 4;
        uchar seq_code : 2;
        // padding
        uchar : 2;
    } p2p;
    struct DOXYNAME(nn) {
        // padding
        uchar : 2;
        uchar route : 3;
        uchar mem_or_normal : 1;
        // padding
        uchar : 2;
    } nn;
    struct DOXYNAME(fr) {
        // padding
        uchar : 4;
        uchar emergency_routing : 2;
        // padding
        uchar : 2;
    } fr;
    uchar value;
} spinnaker_packet_control_byte_t;
 
enum spinnaker_packet_type_t {
    SPINNAKER_PACKET_TYPE_MC = 0,
    SPINNAKER_PACKET_TYPE_P2P = 1,
    SPINNAKER_PACKET_TYPE_NN = 2,
    SPINNAKER_PACKET_TYPE_FR = 3,
};
 
typedef struct {
    // padding
    uint : 16;
    uint control_byte : 8;
    // padding
    uint : 4;
    uint not_full : 1;
    uint overrun : 1;
    uint full : 1;
    uint empty : 1;
} comms_tx_control_t;
 
typedef struct {
    uint multicast : 1;
    uint point_to_point : 1;
    uint nearest_neighbour : 1;
    uint fixed_route : 1;
    // padding
    uint : 12;
    uint control_byte : 8;
    uint route : 3;
    // padding
    uint : 1;
    uint error_free : 1;
    uint framing_error : 1;
    uint parity_error : 1;
    uint received : 1;
} comms_rx_status_t;
 
typedef struct {
    uint p2p_source_id : 16;
    // padding
    uint : 8;
    uint route : 3;
    // padding
    uint : 5;
} comms_source_addr_t;
 
typedef struct {
    comms_tx_control_t tx_control;
    uint tx_data;
    uint tx_key;
    comms_rx_status_t rx_status;
    const uint rx_data;
    const uint rx_key;
    comms_source_addr_t source_addr;
    const uint _test;
} comms_ctl_t;
 
ASSERT_WORD_SIZED(comms_tx_control_t);
ASSERT_WORD_SIZED(comms_rx_status_t);
ASSERT_WORD_SIZED(comms_source_addr_t);
 
static volatile comms_ctl_t *const comms_control = (comms_ctl_t *) CC_BASE;
 
 
// ---------------------------------------------------------------------
// 9. Communications NoC
 
// No registers
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint route_packets_enable : 1;
    uint error_interrupt_enable : 1;
    uint dump_interrupt_enable : 1;
    uint count_timestamp_errors : 1;
    uint count_framing_errors : 1;
    uint count_parity_errors : 1;
    uint time_phase : 2;
    uint monitor_processor : 5;
    // padding
    uint : 2;
    uint reinit_wait_counters : 1;
    uint begin_emergency_wait_time : 8;
    uint drop_wait_time : 8;
} router_control_t;
 
typedef struct {
    uint interrupt_active_for_diagnostic_counter : 16;
    uint busy : 1;
    // padding
    uint : 7;
    uint output_stage : 2;
    // padding
    uint : 3;
    uint interrupt_active_dump : 1;
    uint interrupt_active_error : 1;
    uint interrupt_active : 1;
} router_status_t;
 
enum router_output_stage {
    ROUTER_OUTPUT_STAGE_EMPTY,
    ROUTER_OUTPUT_STAGE_FULL,
    ROUTER_OUTPUT_STAGE_WAIT1,
    ROUTER_OUTPUT_STAGE_WAIT2
};
 
typedef union {
    struct DOXYNAME(flags) {
        // padding
        uint : 6;
        uint time_phase : 2;
        // padding
        uint : 8;
        uint control : 8;
        uint route : 3;
        uint time_phase_error : 1;
        uint framing_error : 1;
        uint parity_error : 1;
        // padding
        uint : 2;
    };
    struct DOXYNAME(control_field_bits) {
        // padding
        uint : 17;
        uint payload : 1;
        // padding
        uint : 4;
        uint type : 2;
    };
    uint word;
} router_packet_header_t;
 
typedef struct {
    uint error_count : 16;
    // padding
    uint : 11;
    uint time_phase_error : 1;
    uint framing_error : 1;
    uint parity_error : 1;
    uint overflow : 1;
    uint error : 1;
} router_error_status_t;
 
typedef struct {
    uint link : NUM_LINKS;
    uint processor : NUM_CPUS;
    // padding
    uint : 8;
} router_dump_outputs_t;
 
typedef struct {
    uint link : NUM_LINKS;
    uint processor : NUM_CPUS;
    // padding
    uint : 6;
    uint overflow : 1;
    uint dumped : 1;
} router_dump_status_t;
 
typedef struct {
    ushort enable;
    ushort reset;
} router_diagnostic_counter_ctrl_t;
 
typedef struct {
    uint enable_cycle_count : 1;
    uint enable_emergency_active_count : 1;
    uint enable_histogram : 1;
    // padding
    uint : 13;
    uint reset_cycle_count : 1;
    uint reset_emergency_active_count : 1;
    uint reset_histogram : 1;
    // padding
    uint : 13;
} router_timing_counter_ctrl_t;
 
typedef struct {
    uint L0 : 2;
    uint L1 : 2;
    uint L2 : 2;
    uint L3 : 2;
    uint L4 : 2;
    uint L5 : 2;
    // padding
    uint : 20;
} router_diversion_t;
 
enum router_diversion_rule_t {
    ROUTER_DIVERSION_NORMAL,
    ROUTER_DIVERSION_MONITOR,
    ROUTER_DIVERSION_DESTROY
};
 
typedef struct {
    uint fr_links : NUM_LINKS;
    uint fr_processors : NUM_CPUS;
    // padding
    uint : 2;
    uint nn_broadcast_links : NUM_LINKS;
} router_fixed_route_routing_t;
 
typedef struct {
    router_control_t control;
    const router_status_t status;
    struct DOXYNAME(error) {
        const router_packet_header_t header;
        const uint key;
        const uint payload;
        const router_error_status_t status;
    } error;
    struct DOXYNAME(dump) {
        const router_packet_header_t header;
        const uint key;
        const uint payload;
        const router_dump_outputs_t outputs;
        const router_dump_status_t status;
    } dump;
    router_diagnostic_counter_ctrl_t diagnostic_counter_control;
    router_timing_counter_ctrl_t timing_counter_control;
    const uint cycle_count;
    const uint emergency_active_cycle_count;
    const uint unblocked_count;
    const uint delay_histogram[16];
    router_diversion_t diversion;
    router_fixed_route_routing_t fixed_route;
} router_t;
 
typedef struct {
    uint type : 4;
    uint emergency_routing : 4;
    uint emergency_routing_mode : 1;
    // padding
    uint : 1;
    uint pattern_default : 2;
    uint pattern_payload : 2;
    uint pattern_local : 2;
    uint pattern_destination : 9;
    // padding
    uint : 4;
    uint counter_event_occurred : 1;
    uint enable_counter_event_interrupt : 1;
    uint counter_event_interrupt_active : 1;
} router_diagnostic_filter_t;
 
typedef union {
    struct DOXYNAME(routes) {
        uint links : NUM_LINKS;
        uint processors : NUM_CPUS;
    };
    uint value;
} router_multicast_route_t;
 
typedef enum {
    ROUTER_P2P_ROUTE_E,
    ROUTER_P2P_ROUTE_NE,
    ROUTER_P2P_ROUTE_N,
    ROUTER_P2P_ROUTE_W,
    ROUTER_P2P_ROUTE_SW,
    ROUTER_P2P_ROUTE_S,
    ROUTER_P2P_ROUTE_DROP,
    ROUTER_P2P_ROUTE_MONITOR
} router_p2p_route;
 
typedef union {
    struct DOXYNAME(routes) {
        router_p2p_route route1 : 3;
        router_p2p_route route2 : 3;
        router_p2p_route route3 : 3;
        router_p2p_route route4 : 3;
        router_p2p_route route5 : 3;
        router_p2p_route route6 : 3;
        router_p2p_route route7 : 3;
        router_p2p_route route8 : 3;
    };
    uint value;
} router_p2p_table_entry_t;
 
ASSERT_WORD_SIZED(router_control_t);
ASSERT_WORD_SIZED(router_packet_header_t);
ASSERT_WORD_SIZED(router_error_status_t);
ASSERT_WORD_SIZED(router_dump_outputs_t);
ASSERT_WORD_SIZED(router_dump_status_t);
ASSERT_WORD_SIZED(router_diagnostic_counter_ctrl_t);
ASSERT_WORD_SIZED(router_timing_counter_ctrl_t);
ASSERT_WORD_SIZED(router_diversion_t);
ASSERT_WORD_SIZED(router_fixed_route_routing_t);
ASSERT_WORD_SIZED(router_diagnostic_filter_t);
ASSERT_WORD_SIZED(router_multicast_route_t);
ASSERT_WORD_SIZED(router_p2p_table_entry_t);
 
static volatile router_t *const router_control = (router_t *) RTR_BASE;
static volatile router_diagnostic_filter_t *const router_diagnostic_filter =
        (router_diagnostic_filter_t *) (RTR_BASE + 0x200);
static volatile uint *const router_diagnostic_counter =
        (uint *) (RTR_BASE + 0x300);
static volatile router_multicast_route_t *const router_multicast_table =
        (router_multicast_route_t *) RTR_MCRAM_BASE;
static volatile uint *const router_key_table = (uint *) RTR_MCKEY_BASE;
static volatile uint *const router_mask_table = (uint *) RTR_MCMASK_BASE;
static volatile router_p2p_table_entry_t *const router_p2p_route_table =
        (router_p2p_table_entry_t *) RTR_P2P_BASE;
 
 
// ---------------------------------------------------------------------
// 11. Inter-chip transmit and receive interfaces
 
// No registers
 
// ---------------------------------------------------------------------
// 12. System NoC
 
// No registers
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint status : 2;
    uint width : 2;
    uint ddr : 3;
    uint chips : 2;
    uint banks : 1;
    uint monitors : 2;
    // padding
    uint : 20;
} sdram_status_t;
 
typedef struct {
    uint command : 3;
} sdram_command_t;
 
enum sdram_command {
    SDRAM_CTL_GO,
    SDRAM_CTL_SLEEP,
    SDRAM_CTL_WAKE,
    SDRAM_CTL_PAUSE,
    SDRAM_CTL_CONFIG,
    SDRAM_CTL_ACTIVE_PAUSE
};
 
typedef struct {
    uint address : 14;
    // padding
    uint : 2;
    uint bank : 2;
    uint cmd : 2;
    uint chip : 2;
    // padding
    uint : 10;
} sdram_direct_command_t;
 
enum sdram_direct_command {
    SDRAM_DIRECT_PRECHARGE = 0,
    SDRAM_DIRECT_AUTOREFRESH = 1,
    SDRAM_DIRECT_MODEREG = 2,
    SDRAM_DIRECT_NOP = 3,
};
 
typedef struct {
    uint column : 3;
    uint row : 3;
    uint auto_precharge_position : 1;
    uint power_down_delay : 6;
    uint auto_power_down : 1;
    uint stop_clock : 1;
    uint burst : 3;
    uint qos : 3;
    uint active : 2;
    // padding
    uint : 9;
} sdram_ram_config_t;
 
typedef struct {
    uint period : 15;
    // padding
    uint : 17;
} sdram_refresh_t;
 
typedef struct {
    uint half_cycle : 1;
    uint cas_lat : 3;
    // padding
    uint : 28;
} sdram_cas_latency_t;
 
typedef struct {
    uint t_dqss;
    uint t_mrd;
    uint t_ras;
    uint t_rc;
    uint t_rcd;
    uint t_rfc;
    uint t_rp;
    uint t_rrd;
    uint t_wr;
    uint t_wtr;
    uint t_xp;
    uint t_xsr;
    uint t_esr;
} sdram_timing_config_t;
 
typedef struct {
    const sdram_status_t status;
    sdram_command_t command;
    sdram_direct_command_t direct;
    sdram_ram_config_t mem_config;
    sdram_refresh_t refresh;
    sdram_cas_latency_t cas_latency;
    sdram_timing_config_t timing_config;
} sdram_controller_t;
 
typedef struct {
    uint enable : 1;
    uint minimum : 1;
    uint maximum : 8;
    // padding
    uint : 22;
} sdram_qos_t;
 
typedef struct {
    uint mask : 8;
    uint match : 8;
    uint orientation : 1;
    // padding
    uint : 15;
} sdram_chip_t;
 
enum sdram_register_maxima {
    SDRAM_QOS_MAX = 15,
    SDRAM_CHIP_MAX = 3
};
 
typedef struct {
    uint meter : 7;
    // padding
    uint : 1;
    uint s0 : 1;
    uint c0 : 1;
    uint s1 : 1;
    uint c1 : 1;
    uint s2 : 1;
    uint c2 : 1;
    uint s3 : 1;
    uint c3 : 1;
    uint decing : 1;
    uint incing : 1;
    uint locked : 1;
    // padding
    uint : 1;
    uint R : 1;
    uint M : 1;
    uint L : 1;
    // padding
    uint : 9;
} sdram_dll_status_t;
 
typedef struct {
    uint s0 : 2;
    uint s1 : 2;
    uint s2 : 2;
    uint s3 : 2;
    uint s4 : 2;
    uint s5 : 2;
    // padding
    uint : 4;
    uint test_decing : 1;
    uint test_incing : 1;
    uint enable_force_inc_dec : 1;
    uint test_5 : 1;
    uint R : 1;
    uint M : 1;
    uint L : 1;
    uint enable_force_lmr : 1;
    uint enable : 1;
    // padding
    uint : 7;
} sdram_dll_user_config0_t;
 
typedef union {
    struct DOXYNAME(tuning) {
        uint tune_0 : 4;
        uint tune_1 : 4;
        uint tune_2 : 4;
        uint tune_3 : 4;
        uint tune_4 : 4;
        uint tune_5 : 4;
        // padding
        uint : 8;
    };
    uint word;
} sdram_dll_user_config1_t;
 
typedef struct {
    const sdram_dll_status_t status;
    sdram_dll_user_config0_t config0;
    sdram_dll_user_config1_t config1;
} sdram_dll_t;
 
ASSERT_WORD_SIZED(sdram_status_t);
ASSERT_WORD_SIZED(sdram_command_t);
ASSERT_WORD_SIZED(sdram_direct_command_t);
ASSERT_WORD_SIZED(sdram_ram_config_t);
ASSERT_WORD_SIZED(sdram_refresh_t);
ASSERT_WORD_SIZED(sdram_cas_latency_t);
ASSERT_WORD_SIZED(sdram_qos_t);
ASSERT_WORD_SIZED(sdram_chip_t);
ASSERT_WORD_SIZED(sdram_dll_status_t);
ASSERT_WORD_SIZED(sdram_dll_user_config0_t);
ASSERT_WORD_SIZED(sdram_dll_user_config1_t);
 
static volatile sdram_controller_t *const sdram_control =
        (sdram_controller_t *) PL340_BASE;
static volatile sdram_qos_t *const sdram_qos_control =
        (sdram_qos_t *) (PL340_BASE + 0x100);
static volatile sdram_chip_t *const sdram_chip_control =
        (sdram_chip_t *) (PL340_BASE + 0x200);
static volatile sdram_dll_t *const sdram_dll_control =
        (sdram_dll_t *) (PL340_BASE + 0x300);
 
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint select : NUM_CPUS;
    // padding
    uint : 2;
    uint security_code : 12;
} sc_magic_proc_map_t;
 
typedef struct {
    uint router : 1;
    uint sdram : 1;
    uint system_noc : 1;
    uint comms_noc : 1;
    uint tx_links : NUM_LINKS;
    uint rx_links : NUM_LINKS;
    uint clock_gen : 1;
    uint entire_chip : 1;
    // padding
    uint : 2;
    uint security_code : 12;
} sc_magic_subsystem_map_t;
 
typedef struct {
    uint reset_code : 3;
    // padding
    uint : 29;
} sc_reset_code_t;
 
enum sc_reset_codes {
    SC_RESET_CODE_POR,
    SC_RESET_CODE_WDR,
    SC_RESET_CODE_UR,
    SC_RESET_CODE_REC,
    SC_RESET_CODE_WDI
};
 
typedef struct {
    uint monitor_id : 5;
    // padding
    uint : 3;
    uint arbitrate_request : 1;
    // padding
    uint : 7;
    uint reset_on_watchdog : 1;
    // padding
    uint : 3;
    uint security_code : 12;
} sc_monitor_id_t;
 
typedef struct {
    uint boot_area_map : 1;
    // padding
    uint : 14;
    uint jtag_on_chip : 1;
    uint test : 1;
    uint ethermux : 1;
    uint clk32 : 1;
    uint jtag_tdo : 1;
    uint jtag_rtck : 1;
    // padding
    uint : 11;
} sc_misc_control_t;
 
typedef union {
    struct DOXYNAME(io_bits) {
        // padding
        uint : 16;
        uint ethernet_receive : 4;
        uint ethernet_transmit : 4;
        uint jtag : 4;
        // padding
        uint : 1;
        uint sdram : 3;
    };
    uint gpio;
} sc_io_t;
 
typedef struct {
    uint input_multiplier : 6;
    // padding
    uint : 2;
    uint output_divider : 6;
    // padding
    uint : 2;
    uint freq_range : 2;
    uint power_up : 1;
    // padding
    uint : 5;
    uint _test : 1;
    // padding
    uint : 7;
} sc_pll_control_t;
 
enum sc_frequency_range {
    FREQ_25_50,
    FREQ_50_100,
    FREQ_100_200,
    FREQ_200_400
};
 
typedef struct {
    uint pa : 2;
    uint adiv : 2;
    // padding
    uint : 1;
    uint pb : 2;
    uint bdiv : 2;
    // padding
    uint : 1;
    uint mem : 2;
    uint mdiv : 2;
    // padding
    uint : 1;
    uint rtr : 2;
    uint rdiv : 2;
    // padding
    uint : 1;
    uint sys : 2;
    uint sdiv : 2;
    // padding
    uint : 7;
    uint invert_b : 1;
} sc_clock_mux_t;
 
enum sc_clock_source {
    CLOCK_SRC_EXT,
    CLOCK_SRC_PLL1,
    CLOCK_SRC_PLL2,
    CLOCK_SRC_EXT4
};
 
typedef struct {
    uint status : NUM_CPUS;
    // padding
    uint : 14;
} sc_sleep_status_t;
 
typedef struct {
    uint temperature : 24;
    uint sample_finished : 1;
    // padding
    uint : 6;
    uint start : 1;
} sc_temperature_t;
 
typedef struct {
    // padding
    uint : 31;
    uint bit : 1;
} sc_mutex_bit_t;
 
typedef struct {
    uint rx_disable : NUM_LINKS;
    // padding
    uint : 2;
    uint tx_disable : NUM_LINKS;
    // padding
    uint : 2;
    uint parity_control : 1;
    // padding
    uint : 3;
    uint security_code : 12;
} sc_link_disable_t;
 
#define _NUM_TEMPS              3
#define _NUM_ARBITERS           32
#define _NUM_LOCK_REGISTERS     32
 
typedef struct {
    const uint chip_id;
    sc_magic_proc_map_t processor_disable;
    sc_magic_proc_map_t set_cpu_irq;
    sc_magic_proc_map_t clear_cpu_irq;
    uint set_cpu_ok;
    uint clear_cpu_ok;
    sc_magic_proc_map_t cpu_soft_reset_level;
    sc_magic_proc_map_t cpu_hard_reset_level;
    sc_magic_subsystem_map_t subsystem_reset_level;
    sc_magic_proc_map_t cpu_soft_reset_pulse;
    sc_magic_proc_map_t cpu_hard_reset_pulse;
    sc_magic_subsystem_map_t subsystem_reset_pulse;
    const sc_reset_code_t reset_code;
    sc_monitor_id_t monitor_id;
    sc_misc_control_t misc_control;
    sc_io_t gpio_pull_up_down_enable;
    sc_io_t io_port;
    sc_io_t io_direction;
    sc_io_t io_set;
    sc_io_t io_clear;
    sc_pll_control_t pll1_freq_control;
    sc_pll_control_t pll2_freq_control;
    uint set_flags;
    uint reset_flags;
    sc_clock_mux_t clock_mux_control;
    const sc_sleep_status_t cpu_sleep;
    sc_temperature_t temperature[_NUM_TEMPS];
    // padding
    const uint _padding[3];
    const sc_mutex_bit_t monitor_arbiter[_NUM_ARBITERS];
    const sc_mutex_bit_t test_and_set[_NUM_LOCK_REGISTERS];
    const sc_mutex_bit_t test_and_clear[_NUM_LOCK_REGISTERS];
    sc_link_disable_t link_disable;
} system_controller_t;
 
enum sc_magic {
    SYSTEM_CONTROLLER_MAGIC_NUMBER = 0x5ec
};
 
ASSERT_WORD_SIZED(sc_magic_proc_map_t);
ASSERT_WORD_SIZED(sc_reset_code_t);
ASSERT_WORD_SIZED(sc_monitor_id_t);
ASSERT_WORD_SIZED(sc_misc_control_t);
ASSERT_WORD_SIZED(sc_io_t);
ASSERT_WORD_SIZED(sc_pll_control_t);
ASSERT_WORD_SIZED(sc_clock_mux_t);
ASSERT_WORD_SIZED(sc_sleep_status_t);
ASSERT_WORD_SIZED(sc_temperature_t);
ASSERT_WORD_SIZED(sc_mutex_bit_t);
ASSERT_WORD_SIZED(sc_link_disable_t);
 
static volatile system_controller_t *const system_control =
        (system_controller_t *) SYSCTL_BASE;
 
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint transmit : 1;
    uint receive : 1;
    uint loopback : 1;
    uint receive_error_filter : 1;
    uint receive_unicast: 1;
    uint receive_multicast : 1;
    uint receive_broadcast : 1;
    uint receive_promiscuous : 1;
    uint receive_vlan : 1;
    uint reset_drop_counter : 1;
    uint hardware_byte_reorder_disable : 1;
    // padding
    uint : 21;
} ethernet_general_command_t;
 
typedef struct {
    uint transmit_active : 1;
    uint unread_counter : 6;
    // padding
    uint : 9;
    uint drop_counter : 16;
} ethernet_general_status_t;
 
typedef struct {
    uint tx_length : 11;
} ethernet_tx_length_t;
 
enum ethernet_tx_length_limits {
    ETHERNET_TX_LENGTH_MIN = 60,
    ETHERNET_TX_LENGTH_MAX = 1514
};
 
typedef struct {
    uint reset : 1;
    uint smi_input : 1;
    uint smi_output : 1;
    uint smi_out_enable : 1;
    uint smi_clock : 1;
    uint irq_invert_disable : 1;
    // padding
    uint : 26;
} ethernet_phy_control_t;
 
typedef struct {
    uint transmit : 1;
    // padding
    uint : 3;
    uint receive : 1;
    // padding
    uint : 27;
} ethernet_interrupt_clear_t;
 
typedef struct {
    uint ptr : 12;
    uint rollover : 1;
    // padding
    uint : 19;
} ethernet_receive_pointer_t;
 
typedef struct {
    uint ptr : 6;
    uint rollover : 1;
    // padding
    uint : 25;
} ethernet_receive_descriptor_pointer_t;
 
typedef struct {
    ethernet_general_command_t command;
    const ethernet_general_status_t status;
    ethernet_tx_length_t transmit_length;
    uint transmit_command;
    uint receive_command;
    uint64 mac_address;
    ethernet_phy_control_t phy_control;
    ethernet_interrupt_clear_t interrupt_clear;
    const ethernet_receive_pointer_t receive_read;
    const ethernet_receive_pointer_t receive_write;
    const ethernet_receive_descriptor_pointer_t receive_desc_read;
    const ethernet_receive_descriptor_pointer_t receive_desc_write;
    uint _test[3];
} ethernet_controller_t;
 
typedef struct {
    uint length : 11;
    // unknown; might be padding or status bits?
    uint : 21;
} ethernet_receive_descriptor_t;
 
ASSERT_WORD_SIZED(ethernet_general_command_t);
ASSERT_WORD_SIZED(ethernet_general_status_t);
ASSERT_WORD_SIZED(ethernet_tx_length_t);
ASSERT_WORD_SIZED(ethernet_phy_control_t);
ASSERT_WORD_SIZED(ethernet_interrupt_clear_t);
ASSERT_WORD_SIZED(ethernet_receive_pointer_t);
ASSERT_WORD_SIZED(ethernet_receive_descriptor_pointer_t);
ASSERT_WORD_SIZED(ethernet_receive_descriptor_t);
 
static volatile uchar *const ethernet_tx_buffer = (uchar *) ETH_TX_BASE;
static volatile uchar *const ethernet_rx_buffer = (uchar *) ETH_RX_BASE;
static volatile ethernet_receive_descriptor_t *const ethernet_desc_buffer =
        (ethernet_receive_descriptor_t *) ETH_RX_DESC_RAM;
static volatile ethernet_controller_t *const ethernet_control =
        (ethernet_controller_t *) ETH_REGS;
 
 
// ---------------------------------------------------------------------
 
typedef struct {
    uint interrupt_enable : 1;
    uint reset_enable : 1;
    // padding
    uint : 30;
} watchdog_control_t;
 
typedef struct {
    uint interrupted : 1;
    // padding
    uint : 31;
} watchdog_status_t;
 
typedef union {
    struct DOXYNAME(fields) {
        uint lock : 1;
        uint magic : 31;
    };
    uint whole_value;
} watchdog_lock_t;
 
enum watchdog_lock_codes {
    WATCHDOG_LOCK_RESET = 0,
    WATCHDOG_LOCK_MAGIC = WD_CODE
};
 
typedef struct {
    uint load;
    const uint value;
    watchdog_control_t control;
    uint interrupt_clear;
    const watchdog_status_t raw_status;
    const watchdog_status_t masked_status;
    // Lots of padding!
    const uint _padding[0x2fa];
    watchdog_lock_t lock;
} watchdog_controller_t;
 
ASSERT_WORD_SIZED(watchdog_control_t);
ASSERT_WORD_SIZED(watchdog_status_t);
ASSERT_WORD_SIZED(watchdog_lock_t);
 
static volatile watchdog_controller_t *const watchdog_control =
        (watchdog_controller_t *) WDOG_BASE;
 
 
// ---------------------------------------------------------------------
// 17. System RAM
 
// No registers
 
// ---------------------------------------------------------------------
// 18. Boot ROM
 
// No registers
 
// ---------------------------------------------------------------------
// 19. JTAG
 
// No registers
 
// ---------------------------------------------------------------------
// 20. Input and Output Signals
 
// No registers
 
// ---------------------------------------------------------------------
// 21. Packaging
 
// No registers
 
// ---------------------------------------------------------------------
// 22. Application Notes
 
// No registers
 
// ---------------------------------------------------------------------
#endif // !__SPINN_EXTRA_H__